1. Field of the Invention
The present invention relates to a memory and a refresh method for memory. More particularly, the present invention relates to a DRAM that is replaceable with SRAM and a method for refreshing such DRAM.
2. Background of the Invention
Since SRAM (static random access memory) can store data with small power, it is widely used as low-power memory. However, SRAM is comprised of six transistors per cell, thus the chip area increases greatly as the storage capacity increases. On the contrary, DRAM (dynamic random access memory) is comprised of one capacitor and one transistor per cell, thus the chip area of the cell for SRAM is 8 to 12 times larger than that of DRAM.
Replacing a low-power SRAM with DRAM has been considered to reduce the chip area. When replacing SRAM with DRAM, a memory that attempts seamless operations in random row access is suitable for this replacement. This memory does not use the conventional page mode and greatly reduces the cycle time by activating blocks on the basis of small array units (i.e., a plurality of blocks are created by dividing an array), and improves the random access performance for row addresses. The size of the block depends on the data storage capacity, that is, the number of cells contained in the array. For a memory that attempts seamless operations in random row access, a flat address is used instead of conventional two addresses RAS (row address strobe) and CAS (column address strobe). The scheme allows small array activation and a reduction in operating current.
However, DRAM needs to be refreshed periodically in order to store data, while refreshing is not required for SRAM. When replacing SRAM with DRAM, the problem is how to perform the refresh.